Please refer to FIG. 1A for a conventional N-channel trench MOSFET structure of prior art (U.S. Pat. No. 6,888,196) with an N+ source regions having same surface doping concentration and junction depth along trenched source-body contact and channel region. The disclosed N-channel trench MOSFET cell is formed in an N epitaxial layer 102 supported on an N+ substrate 100. Near the top surface of a P body region 103, which is formed within said epitaxial layer 102, N+ source region 104 is implanted around the top portion of trenched gates 105 and adjacent to the sidewalls of trenched source-body contact 106. As mentioned above, said N+ source region 104 has a same surface doping concentration and a same junction depth (Ds, as illustrated in FIG. 1A) along epitaxial surface, which is related to the formation process of said N+ source regions 104.
FIG. 1B shows the fabrication method of said N+ source regions 104. After the formation of the P body region 103 and its diffusion, said N+ source regions 104 is formed by performing source Ion Implantation through a source mask (not shown). The top surface of said P body region 103 suffered the same source Ion Implantation and the same N+ dopant diffusion step, therefore said N+ source regions has same doping concentration and same junction depth (Ds, as shown in FIG. 1A) along epitaxial surface.
This uniform distribution of doping concentration and junction depth of said N+ source regions may lead to a hazardous failure during UIS (Unclamped Inductance Switching) test, please refer to FIG. 1C for a top view of said N+ source region 104 and said trenched source-body contact 106 shown in FIG. 1A. As illustrated, Rbc is the base resistance from said trenched source-body contact 106 to the cell corner, Rbe is the base resistance from said trenched source-body contact 106 to the cell edge. Obviously, Rbc is greater than Rbe because the distance from said trenched source-body contact 106 to the cell corner is longer than that from said trenched source-body contact 106 to the cell edge, resulting in said UIS failure occurring at the trench corner and a poor avalanche capability for closed cell at cell corners as the parasitic NPN bipolar transistor is easily turned on.
Accordingly, it would be desirable to provide a new and improved device configuration to avoid the UIS failure occurred at the trench corner in a trench MOSFET while having a better avalanche capability.